The present invention relates in general to data processing systems, and in particular, to the execution of load and store instructions in a processor.
In order to increase the operating speed of microprocessors, architectures have been designed and implemented that allow for the out-of-order execution of instructions within the microprocessor. An advantage of out-of-order execution of instructions is that it allows load miss latencies to be hidden while useful work is being performed. However, traditionally, load and store instructions have not been executed out of order because of the very nature of their purpose. For example, if a store instruction is scheduled to be executed in program order prior to a load instruction, but the processor executes these two instructions out of order so that the load instruction is executed prior to the store instruction, and these two instructions are referring to the same memory space, there is a likelihood that the load instruction will load incorrect, or old, data since the store instruction was not permitted to complete prior to the load instruction.
The above referenced patent applications implement various techniques within a load/store unit for increasing the throughput of instructions through the unit. Within the load/store unit, effective addresses are calculated and utilized. Problems can occur within the load/store unit as a result of effective address (EA) aliasing. EA aliasing is when different EAs point to the same real address (RA). Since the L1 (level 1 or primary) cache is EA addressed (EA 50:51 are not equal to RA 5051), two effective addresses, EA1 and EA2 cannot both be in the cache at the same time. Therefore, what is needed in the art is a technique for dealing with such EA aliasing.
The present invention addresses the foregoing problem by implementing an RA (real address) tag array. When a cache reload occurs, the RA tag array detects the EA alias and clears the cache of the first alias and reloads the cache at the second alias. On aliases, the data is moved by creating a cache miss and reloading from the L2 (level 2 or secondary) cache into the new alias and clearing the old alias. Essentially, the RA tag directory or array is used to handle the aliasing conflicts. The RA tag is also used for snoops. Since the L1 cache is inclusive, if a line is snooped out of the L2 cache, the corresponding line in the L1 cache must be invalidated. The occurrence of the cache line in the directories is found using the RA tag in the RA tag array.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.